With the size of CMOS device being continuously scaled down, the influences of the short channel effect and the charge carrier mobility deterioration effect in the device are increasingly serious. With respect to the development of the silicon based CMOS technology, the requirements for the ability of suppressing the short channel effect and the ability of improving the charge carrier mobility in the device become more and more urgent.
In order to suppress the short channel effect, conventional methods mainly include increasing the doping concentration in a substrate, adding source/drain lightly doping region (LDD region), and introducing a pocket structure, etc; meanwhile, an ultra thin body structure may also be adopted in a silicon-on-insulator (SOI) device. However, to increase the doping concentration in a substrate will increase the threshold voltage and reduce the on-state current, to add the LDD region will increase the parasitic resistance, and to introduce the pocket structure may also result in the increasing of the doping level in the substrate; meanwhile, to adopt the ultra thin body structure may result in the increasing of source/drain series resistance, and at the same time the charge carrier mobility in the channel and the over-driving ability of the device will be greatly reduced due to the increasing of interface scattering and the self-heating effect, etc. In order to solve these technical contradictions, China patent publication CN1450653A suggests a quasi SOI device structure, as shown in FIG. 1, the key structure of which is an “L” shaped local insulation layer isolation wall 8 that is arranged between the source/drain and the body region and enveloping the source/drain; the ability of suppressing short channel effect of the device can be improved effectively by using the isolation wall instead of conventional pn junction isolation between the source/drain and the body region.
Meanwhile, when the feature size of a device enters into sub-100 nm regime, the short channel effect of the device is deteriorated, so that the method for obtaining better performance by further reducing the size of the device becomes extremely difficult. In order to relieve the pressure resulted from the reduction of the device size, stress is introduced into a channel by adopting strained-silicon technology so as to improve the charge carrier mobility in the channel and the performance of a transistor device, which has become a method widely adopted and indispensable in the engineering of microelectronic fabrication. Its basic principle is that, stress is introduced into a channel region of a transistor by means of the device structure, material and process design so that the lattice structure of crystals is varied, and thus leads to the variation of the charge carrier mobility. Under appropriate stress, charge carrier mobility may be improved. For example, the tensile stress in the channel direction may improve the electron mobility, and the compressive stress in the channel direction may improve the hole mobility.
It is critical for the strain technology that how to introduce the stress that is necessary to a device into a channel. The conventional methods for introducing stress mainly include:
1. Strain is produced in the channel portion by means of Si/SiGe heterojunction substrate structure. As shown in FIG. 2a, by adopting a non-silicon substrate, such as a SiGe substrate, stress is applied to the channel layer by means of the lattice difference between the substrate 10 and the surface Si channel layer. Since the lattice constant of SiGe is larger than that of Si, the lattice of the surface Si channel layer are stretched by the SiGe lattice of bottom layer in this case, so that stress is introduced into the Si channel.
2. Stress is introduced into the channel portion by means of heterojunction source/drain structure, that is, the Si material of the source/drain region is replaced by a non-silicon (non-Si) material, and stress is induced in the channel by means of the heterojunction between the source/drain and the channel. As shown in FIG. 2b, source/drain 12 is formed of SiGe having a large lattice, thus stress may be introduced in the channel direction.
3. Stress is introduced into the channel and the substrate by covering a high stress layer over the device, that is, a high stress thin film 13 is covered over the device, and deformation of the device under the thin film is induced by the deformation of the thin film itself, so that stress is introduced into the channel, as shown in FIG. 2c. 
It is noted that the above mentioned methods for introducing stress into the channel have changed the mobility of charge carrier, but do not fundamentally improve the device structure, and thus can not effectively improve the short channel effect suppressing ability of the device itself.